The present disclosure relates to a semiconductor device having a structure in which an insulator layer and a semiconductor layer are laminated on a semiconductor substrate.
For semiconductor integrated circuits including a complementary metal oxide semiconductor (CMOS) transistor, it has been studied to achieve high integration and a high operating speed. In recent years, development of CMOS large-scale integrated circuits (CMOS-LSIs) having a silicon-on-insulator (SOI) structure of low power consumption and a high operating speed has been in progress.
In a CMOS-LSI, a large amount of heat is generated, in particular, in an active region of a metal-oxide-semiconductor field-effect transistor (MOSFET). This amount of generated heat may reach tens of watts, and the temperature of the CMOS-LSI may increase from tens of degrees Celsius to nearly one hundred degrees Celsius, in some cases. Such an increase in temperature may bring disadvantages due to a self-heating effect. Examples of such disadvantages may include a disadvantage of a reduction in an ON-state current of the MOSFET due to a decrease in mobility of a carrier, and a disadvantage of an increase in propagation delay by metal wiring due to an increase in resistance value of the metal wiring. In this regard, in an ordinary CMOS-LSI not having the SOI structure, heat generated in an active region of a MOSFET is immediately dissipated from a package containing a semiconductor chip, mainly through a semiconductor substrate having high thermal conductivity (for example, a silicon substrate). In contrast, in the CMOS-LSI having the SOI structure, the heat generated in the active region of the MOSFET is not easily released to outside, because an insulator layer having low thermal conductivity (for example, a silicon oxide layer) is present between the active region of the MOSFET and a semiconductor substrate. Therefore, the above-described disadvantages are easily invited.
Thus, there has been disclosed a technique of securing a heat dissipation path by, for example, allowing one end of a contact plug connected to a diffusion layer to pass through a silicon oxide film, to be brought into contact with a silicon substrate (for example, see Japanese Unexamined Patent Application Publication No. H11-135799).